This invention relates to a bit error correcting circuit for a nonvolatile semiconductor programmable read-only memory (hereafter ROM) such as an electrically erasable and programmable ROM (hereafter EEPROM).
An EEPROM includes a storage MOS transistor as a memory cell and a sense amplifier. The storage MOS transistor has a thin oxide film (tunneling oxide film) and a floating gate. The arrangement and operation of the EEPROM is described in, for example, "16K Bit EEPROM Electrically Erasable In a Bit Unit", Nikkei Electronics, Jun. 23, 1980, pp. 198 to 207 and Japanese Laid-open Patent Application No. 1987/32823.
FIG. 1 shows typical characteristics of the memory cell of an EEPROM. A threshold voltage of the memory cell might change due to leakage of charge. Such leakage may be caused by degradation of the breakdown voltage of the tunneling oxide film after a large number of write-erase cycles, or by a pinhole of the tunneling oxide film. A threshold voltage Vt1 of the memory cell in a write state is about -2 V. On the other hand, a threshold voltage Vt2 of the memory cell in an erase state is about 8 V. When the threshold voltage Vt1 is deteriorated, it changes from about -2 V to about 2 V as shown at (a). When the threshold voltage Vt2 is deteriorated, it changes from about 8 V to about 2 V as shown at (b).
The sense amplifier of the EEPROM detects the threshold voltage of the memory cell and outputs data. When the threshold voltage Vt1 is lower than a sense voltage Vr, the sense amplifier outputs "1". On the other hand, when the threshold voltage Vt1 is not lower than the sense voltage Vr, the sense amplifier outputs "0". Therefore, when a low sense voltage Vr1, for example 1 V, is applied in case of the deterioration of the memory cell in write state, the output data is changed from "1" to "0". However, when a high sense voltage Vr2, for example 4 V, is applied in case of the deterioration of the memory cell in the write state, the output data is unchanged.
U.S. Pat. No. 4,901,320 discloses a bit error correcting circuit incorporated in a microcomputer. The disclosed bit error detecting circuit uses two different sense voltages and detects and corrects the error of the memory cell by a special program in the microcomputer. The disclosed bit error circuit needs special control signals such as EACC, WACC, EROM etc., as set forth at column 11 lines 28-36 of the specification. Further, the disclosed bit error detecting circuit has complex hardware as shown in FIGS. 6 and 7. Furthermore, the disclosed EEPROM has only one addressing mode because of the complex hardware of the bit error correcting circuit.